BCD to 7 Segment Decoder The BCD to 7 Segment Decoder converts 4 bit binary to 7 bit control signal which can be displayed on 7 segment display. Seven display consist of 7 led segments to display 0 to 9 and A to F. VHDL Code BCD to 7 Segment Display decoder can be implemented
Mealy State Machine The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input. Moore State Machine The Output of the State machine depends only on present state. The output of state machine are only
Carry Select Adder Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input ‘0’ and select Sum and carry output from stage 2 ripple carry adder, when carry input ‘1’.
Carry Save Adder Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage. At first stage result carry is not propagated through addition operation. In order to generate carry, implemented ripple carry adder on stage 2
Carry Look Ahead Adder Carry Look Ahead Adder is fastest adder compared Ripple carry Adder. For the Purpose of carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and generation Carry block. It avoid Carry propagation through each adder. In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then
Ripple Carry Adder Ripple Carry Adder adds 2 n-bit number plus carry input and gives n-bit sum and a carry output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin)
Ring Counter Ring Counter very similar to shift register. At each clock pulse, data at each flipflop shifted to next flipflop with last output is feed back to the input of first flipflop. Also the first flop is set to ‘1’ at the reset state. so it shift bit ‘1’ to next flipflop for each clock