Last updated on June 8th, 2016 at 04:11 amReset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset. Asynchronous Reset Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input.
Last updated on July 18th, 2017 at 11:40 pmBinary to BCD Converter Some times we need to display the output in a seven-segment display. For that purpose we will convert binary to BCD. To translate from binary to BCD, we can employ the shift-and-add-3 algorithm: Left-shift the (n-bit) binary number one bit. If n shifts
Last updated on May 19th, 2016 at 08:51 pmBlock RAM: Xilinx FPGA Consist of 2 columns of memory called Block RAM or BRAM. It is a Dual port memory with separate Read/Write port. It can be configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on. BRAM can be excellent for FIFO implementation. Multiple
Last updated on June 9th, 2015 at 03:26 pmBinary comparator compare two 4-bit binary number. It is also known as magnitude comparator and digital comparator. Analog form comparator is voltage comparator. The functionality of this comparator circuit is, It consist of 3 outputs Greater, Equal and Smaller. If inp-A is greater then inp-B then greater
Last updated on May 19th, 2016 at 08:06 pmThis example describes a two input 4-bit adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an OP input. 0 input produce adder output and 1 input produce subtractor output. VHDL Code for 4-bit Adder / Subtractor
Last updated on July 18th, 2017 at 11:54 pmAll flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. SR FlipFlop A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown
Last updated on July 18th, 2017 at 11:57 pmClock Divider Clock Divider is also known as frequency divider, which divides the input clock frequency and produce output clock. In our case let us take input frequency as 50MHz and divide the clock frequency to generate 1KHz output signal. VHDL code consist of Clock and Reset