Author: Admin

VHDL Component and Port Map Tutorial

Last updated on July 21st, 2017 at 06:35 amVHDL Port Map and Component Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease. Instead of coding a complex design in single VHDL Code. we can divide

FPGA Design Flow

Last updated on June 6th, 2015 at 03:29 amIn this part of tutorial we are going to have a short intro on FPGA design flow. A simplified version of FPGA design flow is given in the flowing diagram. Design Entry There are different techniques for design entry. Schematic based, Hardware Description Language and combination of

VHDL Code for Full Adder

Last updated on October 14th, 2017 at 05:44 pmFull Adder The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are

VHDL Code for 4-Bit Binary Up Counter

Last updated on July 24th, 2015 at 01:53 pmThe clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). VHDL Code for 4-bit binary counter