Category: VHDL

VHDL Code for 2 to 4 decoder

Last updated on July 18th, 2017 at 10:05 pmBinary decoder Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling.

VHDL Code for 4 to 2 Encoder

Last updated on July 25th, 2017 at 12:10 amBinary Encoder Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling. 4 to 2 encoder design using logic gates Truth Table

VHDL Code for 4-Bit Aynchronous Accumulator

Last updated on July 18th, 2017 at 10:10 pmAccumulator Accumulator work similar to the functionality of counter. The main difference is instead increment the counter value by constant, Accumulator add the input value with the current value. Accumulator Block Diagram VHDL Code for 4-bit Asynchronous Accumulator TestBench VHDL Code for 4-bit Asynchronous Accumulator Output Waveform for

VHDL code for 1 to 4 Demux

Last updated on July 28th, 2017 at 12:12 pmDeMultiplexer Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single input through selection line. It consist of  1 input and 2 power n output. The output data lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to

VHDL 4 to 1 Mux (Multiplexer)

Last updated on July 18th, 2017 at 11:23 pmMultiplexer Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line through selection line. It consist of 2 power n input and 1 output. The input data lines are controlled by n selection lines. For Example, if n = 2 then the mux will

VHDL Code for Debounce Circuit in FPGA

Last updated on July 18th, 2017 at 11:32 pmDebounce Push Button always got the mechanical property of bouncing state at micro sec. The above figure describes the debouncing  output result,  when the Push Button is pressed. When you pull down the push button from high to low state. It bounce back to high and low few

Synchronous and Asynchronous Reset VHDL

Last updated on June 8th, 2016 at 04:11 amReset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset. Asynchronous Reset Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input.