Category: VHDL

VHDL Testbench Tutorial

VHDL Testbench VHDL Testbench is important part of VHDL design to check the functionality of Design through simulation waveform. Testbench provide stimulus for design under test DUT or Unit Under Test UUT to check the output result. A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli that

VHDL Component and Port Map Tutorial

VHDL Port Map and Component Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease. Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component

VHDL Code for Full Adder

Full Adder The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are High. Cout is High, when two or more