FPGA and VHDL Tutorials Blog

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VHDL Code for 4-Bit Shift Register

VHDL Code for shift register can be categorised in serial in serial out shift register, serial in parallel out shift register, parallel in parallel out shift register and parallel in serial out shift register. Parallel In – Parallel Out ShiftRead More »

VHDL Testbench Tutorial 0

VHDL Testbench Tutorial

VHDL Testbench is important part of VHDL design to check the functionality of Design through simulation waveform. Testbench provide stimulus for design under test DUT or Unit Under Test UUT to check the output result. A test bench is HDLRead More »

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FPGA Configuration Tutorial

What is FPGA Configuration? The FPGA is made of SRAM (Volatile Memory) so the data configured inside FPGA lost at power Off state. FPGA Configuration is the process of loading the FPGA chip with Configuration data through external devices during power On state. TheRead More »

Field Programmable Gate Array 0

FPGA Architecture

Field-programmable gate array (FPGA) is a device that has array of Configurable logic gates and can be programmed on-board through dedicated Joint Test Action Group (JTAG) or through any other serial/ Parallel non-volatile Memory. FPGA architecture are based on static random-accessRead More »

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VHDL Component and Port Map Tutorial

Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease. Instead of coding a complex design in single VHDL Code. weRead More »

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FPGA Design Flow

In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified version of FPGA design flow is given in the flowing diagram. Design Entry There are different techniques for design entry. SchematicRead More »

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VHDL Code for Full Adder

The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High whenRead More »