Setup Time and Hold Time in FPGA

Setup Time The amount of time the synchronous input (D) must be stable before the active edge of the clock. Hold Time The amount of time the synchronous input (D) must be stable after the active edge of the clock. Metastability If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is

Digital Clock manager DCM in Xilinx FPGA

Digital Clock Manager DCM provides clocking to all the resources of Xilinx FPGA with advanced feature. Digital Clock Manager DCM integrates advanced clocking capabilities to FPGA global clock distribution network. It eliminates clock deskewing, Phase shifting, and also act as frequency synthesizer multiply/divide input clock. Clock Deskewing The Delay-Locked Loop (DLL) unit provides an on-chip digital

VHDL code for 4-bit ALU

ALU ALU’s comprise the combinational logic that implements logic operations such as AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor. Functionally, the operation of typical ALU is represented as shown in diagram below, Functional Description of 4-bit Arithmetic Logic Unit Controlled by the three function select inputs (sel 2 to 0), ALU can

VHDL Code for 4-Bit Shift Register

Shift Register VHDL Code for shift register can be categorised in serial in serial out shift register, serial in parallel out shift register, parallel in parallel out shift register and parallel in serial out shift register. Parallel In – Parallel Out Shift Registers For parallel in – parallel out shift registers, all data bits appear

VHDL Testbench Tutorial

VHDL Testbench VHDL Testbench is important part of VHDL design to check the functionality of Design through simulation waveform. Testbench provide stimulus for design under test DUT or Unit Under Test UUT to check the output result. A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli that

FPGA Configuration Tutorial

What is FPGA Configuration? The FPGA is made of SRAM (Volatile Memory) so the data configured inside FPGA lost at power Off state. FPGA Configuration is the process of loading the FPGA chip with Configuration data through external devices during power On state. The Method of Configuring FPGA Can be divided in to Master Mode Slave Mode JTAG Mode

FPGA Architecture

What is FPGA? Field-programmable gate array (FPGA) is a device that has array of Configurable logic gates and can be programmed on-board through dedicated Joint Test Action Group (JTAG) or through any other serial/ Parallel non-volatile Memory. FPGA architecture are based on static random-access memory (SRAM) Volatile memory. The Data programmed inside the memory of an FPGA