VHDL Component and Port Map Tutorial

VHDL Port Map and Component Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease. Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component

FPGA Design Flow

In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified version of FPGA design flow is given in the flowing diagram. Design Entry There are different techniques for design entry. Schematic based, Hardware Description Language and combination of both etc. . Selection of a method depends

VHDL Code for Full Adder

Full Adder The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are High. Cout is High, when two or more