VHDL Code for 4-bit Adder / Subtractor

November 17, 2020August 2, 2014 by Support Team

This example describes a two input 4-bit adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an OP input. 0 input produce adder output and 1 input produce subtractor output.

VHDL Code for 4-bit Adder / Subtractor

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