Tutorial 3: ALU Structural Modelling FPGA Implementation

ALU ALU internally always do multiple operations like addition, subtraction, division and multiplication. We have to specify which result you want to return as an output by using control lines. In this tutorial, We are implementing 3 bit ALU with Adder, Subtractor, Multiplier and comparator. To perform this ALU Demo, we are using Slide Switch … Read moreTutorial 3: ALU Structural Modelling FPGA Implementation

Tutorial 1: Binary Counter FPGA Implementation

In this tutorial, We implemented 4 bit binary counter using EDGE Spartan 6 FPGA Kit. It counts at every 0.5 sec. We already designed 4 bit Binary counter for simulation which counts at input clock frequency (20 ns). As a result we can’t visually differentiate the counting sequence with on-board LEDs as it is counting … Read moreTutorial 1: Binary Counter FPGA Implementation

Sequence Detector using Mealy and Moore State Machine VHDL Codes

Mealy State Machine
The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input.
Moore State Machine
The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.