## Tutorial 3: ALU Structural Modelling FPGA Implementation

By shahul akthar
/
November 8, 2018

ALU ALU internally always do multiple operations like addition, subtraction, division and multiplication. We have to specify which result you...

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## Tutorial 2: BCD to 7 Segment FPGA Implementation

By shahul akthar
/
November 4, 2018

EDGE Spartan 6 FPGA Development Board consist of 16 No. of slide switches and 4 digit seven segment display. Lets...

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## Tutorial 1: Binary Counter FPGA Implementation

By shahul akthar
/
November 4, 2018

In this tutorial, We implemented 4 bit binary counter using EDGE Spartan 6 FPGA Kit. It counts at every 0.5...

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## Introducing EDGE Spartan 6 FPGA Development Board!

By shahul akthar
/
February 1, 2018

All About FPGA brings you a feature rich development board for FPGA learners community. EDGE Spartan 6 FPGA Development board...

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## BCD to 7 Segment Decoder VHDL Code

By shahul akthar
/
July 9, 2017

VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design.
For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.

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## Sequence Detector using Mealy and Moore State Machine VHDL Codes

By shahul akthar
/
July 5, 2017

Mealy State Machine
The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input.
Moore State Machine
The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.

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## Carry Select Adder VHDL Code

By shahul akthar
/
June 2, 2016

Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input '0' and select Sum and carry output from stage 2 ripple carry adder, when carry input '1'.

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## Carry Save Adder VHDL Code

By shahul akthar
/
May 31, 2016

Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage. At first stage result carry is not propagated through addition operation. In order to generate carry, implemented ripple carry adder on stage 2 for carry propagation. Carry Save adder VHDL Code can be constructed by port mapping full adder VHDL Code to 2 stage adder circuit.

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## Carry Look Ahead Adder VHDL Code

By shahul akthar
/
May 29, 2016

Carry Look Ahead Adder is fastest adder compared Ripple carry Adder. For the Purpose of carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and generation Carry block. It avoid Carry propagation through each adder.
In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then Carry logic using Propagation and generation Block.

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## 4 Bit Ripple Carry Adder VHDL Code

By shahul akthar
/
May 29, 2016

Ripple Carry Adder adds 2 n-bit number plus carry input and gives n-bit sum and a carry output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin) input and (Sum, Cout) output. The 4-bit Ripple Carry Adder VHDL Code can be Easily Constructed by Port Mapping 4 Full Adder. The following figure represent the 4-bit ripple carry adder.

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## VHDL Code for 4-bit Ring Counter and Johnson Counter

By shahul akthar
/
May 22, 2016

Ring Counter very similar to shift register. At each clock pulse, data at each flipflop shifted to next flipflop with last output is feed back to the input of first flipflop. Also the first flop is set to '1' at the reset state. so it shift bit '1' to next flipflop for each clock input and repeat the sequence as shown below.

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## VHDL Code for 2 to 4 decoder

By shahul akthar
/
February 6, 2016

Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling.

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## VHDL Code for 4 to 2 Encoder

By shahul akthar
/
February 5, 2016

Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling.

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## VHDL Code for 4-Bit Aynchronous Accumulator

By shahul akthar
/
February 4, 2016

Accumulator work similar to the functionality of counter. The main difference is instead increment the counter value by constant, Accumulator add the input value with the current value.

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## VHDL code for 1 to 4 Demux

By shahul akthar
/
February 2, 2016

Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single input through selection line. It consist of 1 input and 2 power n output. The output data lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to 4 mux with 1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4 Demux described below.

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## VHDL 4 to 1 Mux (Multiplexer)

By shahul akthar
/
January 29, 2016

Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line through selection line. It consist of 2 power n input and 1 output. The input data lines are controlled by n selection lines.

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## Xilinx Chipscope Pro Tutorial

By shahul akthar
/
July 21, 2015

This Xilinx Chipscope Pro Tutorial provides you step by step procedure to debug your FPGA Design internal signal. This procedure...

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## ModelSim Tutorial – Write Complie and Simulate Verilog

By shahul akthar
/
July 9, 2015

ModelSim Tutorial - Write Complie and Simulate Verilog

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## Xilinx System Generator Matlab Tutorial

By shahul akthar
/
July 7, 2015

This Xilinx System Generation Matlab tutorial help you to familiar with Introduction to Xilinx System generator Xilinx Toolbox in Simulink Programming...

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## Working with Altera Quartus II Software

By shahul akthar
/
July 6, 2015

This Video demonstrate step by step procedure to create new Altera Quartus II Project with Schematics for NAND gate logic...

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