Introducing EDGE Spartan 6 FPGA Development Board!
FPGA

Introducing EDGE Spartan 6 FPGA Development Board!

All About FPGA brings you a feature rich development board for FPGA learners community. EDGE Spartan 6 FPGA Development board...
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BCD to 7 Segment Decoder VHDL Code
VHDL

BCD to 7 Segment Decoder VHDL Code

VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design. For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.
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Sequence Detector using Mealy and Moore State Machine VHDL Codes
VHDL

Sequence Detector using Mealy and Moore State Machine VHDL Codes

Mealy State Machine The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input. Moore State Machine The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.
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Carry Select Adder VHDL Code
VHDL

Carry Select Adder VHDL Code

Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input '0' and select Sum and carry output from stage 2 ripple carry adder, when carry input '1'.
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Carry Save Adder VHDL Code
VHDL

Carry Save Adder VHDL Code

Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage.  At first stage result carry is not propagated through  addition operation. In order to generate carry, implemented ripple carry adder on stage 2 for carry propagation. Carry Save adder VHDL Code can be constructed by port mapping full adder VHDL Code to 2 stage adder circuit.
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Carry Look Ahead Adder VHDL Code
VHDL

Carry Look Ahead Adder VHDL Code

Carry Look Ahead Adder is fastest adder compared Ripple carry Adder. For the Purpose of carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and generation Carry block. It avoid Carry propagation through each adder. In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then Carry logic using Propagation and generation Block.
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4 Bit Ripple Carry Adder VHDL Code
VHDL

4 Bit Ripple Carry Adder VHDL Code

Ripple Carry Adder adds 2 n-bit number plus carry input  and gives n-bit sum and a carry output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin) input and (Sum, Cout) output.  The 4-bit Ripple Carry Adder VHDL Code can be Easily Constructed by Port Mapping 4 Full Adder. The following figure represent the 4-bit ripple carry adder.
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VHDL Code for 4-bit Ring Counter and Johnson Counter
VHDL

VHDL Code for 4-bit Ring Counter and Johnson Counter

Ring Counter very similar to shift register. At each clock pulse, data at each flipflop shifted to next flipflop with last output is feed back to the input of first flipflop. Also the first flop is set to '1' at the reset state. so it shift bit '1' to next flipflop for each clock input and repeat the sequence as shown below.
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VHDL Code for 2 to 4 decoder
VHDL

VHDL Code for 2 to 4 decoder

Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling.
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VHDL Code for 4 to 2 Encoder
VHDL

VHDL Code for 4 to 2 Encoder

Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling.
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VHDL Code for 4-Bit Aynchronous Accumulator
VHDL

VHDL Code for 4-Bit Aynchronous Accumulator

Accumulator work similar to the functionality of counter. The main difference is instead increment the counter value by constant, Accumulator add the input value with the current value.
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VHDL code for 1 to 4 Demux
VHDL

VHDL code for 1 to 4 Demux

Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single input through selection line. It consist of  1 input and 2 power n output. The output data lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to 4 mux with 1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4 Demux described below.
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VHDL 4 to 1 Mux (Multiplexer)
VHDL

VHDL 4 to 1 Mux (Multiplexer)

Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line through selection line. It consist of 2 power n input and 1 output. The input data lines are controlled by n selection lines.
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Xilinx Chipscope Pro Tutorial
Xilinx Tutorial

Xilinx Chipscope Pro Tutorial

This Xilinx Chipscope Pro Tutorial provides you step by step procedure to debug your FPGA Design internal signal. This procedure...
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ModelSim Tutorial – Write Complie and Simulate Verilog
Simulation Tutorial

ModelSim Tutorial – Write Complie and Simulate Verilog

ModelSim Tutorial - Write Complie and Simulate Verilog
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Xilinx System Generator Matlab Tutorial
Xilinx Tutorial

Xilinx System Generator Matlab Tutorial

This Xilinx System Generation Matlab tutorial help you to familiar with Introduction to Xilinx System generator Xilinx Toolbox in Simulink Programming...
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Working with Altera Quartus II Software
Altera Tutorial

Working with Altera Quartus II Software

This Video demonstrate step by step procedure to create new Altera Quartus II Project with Schematics for NAND gate logic...
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Working with Xilinx ISE Software
Xilinx Tutorial

Working with Xilinx ISE Software

This Video demonstrate step by step procedure to create new Xilinx ISE Project with VHDL top module for LED Blinking...
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What is FPGA?
FPGA Video Tutorial

What is FPGA?

After watching this FPGA Basics video you will be able to understand what is FPGA? How to configure FPGA? Difference...
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VHDL Basics Part-8
VHDL Video Tutorial

VHDL Basics Part-8

This Video tutorial introduce basic VHDL to the Beginners. Part-8
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