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Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board
FPGA FPGA Video Tutorial

Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board

In this IoT project, we are Monitoring Temperature, Light Intensity and control the home appliances such as air conditioner and...
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Social distancing with Gesture based door/light control using Edge Artix 7 FPGA board
FPGA FPGA Video Tutorial

Social distancing with Gesture based door/light control using Edge Artix 7 FPGA board

In this project, we have implemented the hand gesture based Door open/close and Light on/off system using Edge Artix 7...
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IoT Covid19 updates in 2×16 LCD and VGA Monitor using EDGE Artix 7 FPGA kit
FPGA VHDL

IoT Covid19 updates in 2×16 LCD and VGA Monitor using EDGE Artix 7 FPGA kit

This project visualizes the current data of the coronavirus outbreak of India in real-time on a VGA monitor and also...
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Introduction and Advantages of Digital Sensor Addon for EDGE FPGA kit
FPGA FPGA Video Tutorial VHDL

Introduction and Advantages of Digital Sensor Addon for EDGE FPGA kit

Digital Sensor Addon card is designed to interface 4 digital sensor modules to EDGE FPGA kits. Those sensor includes 3...
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Introducing Motor Drive Addon for EDGE FPGA kit
FPGA FPGA Video Tutorial VHDL Xilinx Tutorial

Introducing Motor Drive Addon for EDGE FPGA kit

Invent Logics bring you the motor driver interface card with motors and relay module. This motor driver can be directly...
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FPGA Implementation of Internet of Things (IoT)
FPGA

FPGA Implementation of Internet of Things (IoT)

Internet of Things IoT is the way of connecting physical objects with IP address to the cloud or any other...
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Tutorial 3: ALU Structural Modelling FPGA Implementation
FPGA VHDL

Tutorial 3: ALU Structural Modelling FPGA Implementation

ALU ALU internally always do multiple operations like addition, subtraction, division and multiplication. We have to specify which result you...
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Tutorial 2: BCD to 7 Segment FPGA Implementation
FPGA VHDL

Tutorial 2: BCD to 7 Segment FPGA Implementation

EDGE Spartan 6 FPGA Development Board consist of 16 No. of slide switches and 4 digit seven segment display. Lets...
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Tutorial 1: Binary Counter FPGA Implementation
FPGA VHDL

Tutorial 1: Binary Counter FPGA Implementation

In this tutorial, We implemented 4 bit binary counter using EDGE Spartan 6 FPGA Kit. It counts at every 0.5...
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Introducing EDGE Spartan 6 FPGA Development Board!
FPGA

Introducing EDGE Spartan 6 FPGA Development Board!

All About FPGA brings you a feature rich development board for FPGA learners community. EDGE Spartan 6 FPGA Development board...
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BCD to 7 Segment Decoder VHDL Code
VHDL

BCD to 7 Segment Decoder VHDL Code

VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design. For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.
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Sequence Detector using Mealy and Moore State Machine VHDL Codes
VHDL

Sequence Detector using Mealy and Moore State Machine VHDL Codes

Mealy State Machine The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input. Moore State Machine The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.
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Carry Select Adder VHDL Code
VHDL

Carry Select Adder VHDL Code

Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input '0' and select Sum and carry output from stage 2 ripple carry adder, when carry input '1'.
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Carry Save Adder VHDL Code
VHDL

Carry Save Adder VHDL Code

Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage.  At first stage result carry is not propagated through  addition operation. In order to generate carry, implemented ripple carry adder on stage 2 for carry propagation. Carry Save adder VHDL Code can be constructed by port mapping full adder VHDL Code to 2 stage adder circuit.
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Carry Look Ahead Adder VHDL Code
VHDL

Carry Look Ahead Adder VHDL Code

Carry Look Ahead Adder is fastest adder compared Ripple carry Adder. For the Purpose of carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and generation Carry block. It avoid Carry propagation through each adder. In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then Carry logic using Propagation and generation Block.
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4 Bit Ripple Carry Adder VHDL Code
VHDL

4 Bit Ripple Carry Adder VHDL Code

Ripple Carry Adder adds 2 n-bit number plus carry input  and gives n-bit sum and a carry output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin) input and (Sum, Cout) output.  The 4-bit Ripple Carry Adder VHDL Code can be Easily Constructed by Port Mapping 4 Full Adder. The following figure represent the 4-bit ripple carry adder.
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VHDL Code for 4-bit Ring Counter and Johnson Counter
VHDL

VHDL Code for 4-bit Ring Counter and Johnson Counter

Ring Counter very similar to shift register. At each clock pulse, data at each flipflop shifted to next flipflop with last output is feed back to the input of first flipflop. Also the first flop is set to '1' at the reset state. so it shift bit '1' to next flipflop for each clock input and repeat the sequence as shown below.
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VHDL Code for 2 to 4 decoder
VHDL

VHDL Code for 2 to 4 decoder

Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling.
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VHDL Code for 4 to 2 Encoder
VHDL

VHDL Code for 4 to 2 Encoder

Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling.
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VHDL Code for 4-Bit Aynchronous Accumulator
VHDL

VHDL Code for 4-Bit Aynchronous Accumulator

Accumulator work similar to the functionality of counter. The main difference is instead increment the counter value by constant, Accumulator add the input value with the current value.
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