VHDL Component and Port Map Tutorial
Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease.
Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component and combine them using Port Map technique.
VHDL Port Map is the Process of mapping the input/ Output Ports of Component in Main Module.