Block RAM and Distributed RAM in Xilinx FPGA

Last updated on May 19th, 2016 at 08:51 pm

Block RAM:

  • Xilinx FPGA Consist of 2 columns of memory called Block RAM or BRAM.
  • It is a Dual port memory with separate Read/Write port.
  • It can be  configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on.
  • BRAM can be excellent for FIFO implementation.
  • Multiple blocks can be cascaded to create still larger memory.
  • The block RAM functions as dual or single-port memory.
  •  The maximum data path width of the block RAM is 18 bits.


Distributed RAM:

  • CLB LUT configurable as Distributed RAM
  • A LUT equals 16×1 RAM
  • Implements Single and DualPorts
  • Cascade LUTs to increase RAM size
  • Synchronous write and Synchronous/Asynchronous read

Distributed RAM

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