VHDL Component and Port Map Tutorial

Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease.

Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component and combine them using Port Map technique.

VHDL Port Map is the Process of mapping the input/ Output Ports of Component in Main Module.

VHDL Component and Port Map

There are 2 ways we can Port Map the Component in VHDL Code. They are

  • Positional Port Map
  • Nominal Port Map

Positional Port Map maps the formal in/out port location with actual in/out port without changing its location.

For example:

Component and_gate

port( x,y: in std_logic;

z: out std_logic);

end component;

a1: and_gate port map(a,b,out);

Nominal Port Map assign the formal parameter with actual parameter as shown below.

a1: and_gate port map(a => x, b => y, out =>z);

Let’s Create sample Component and Port Map in Main VHDL Module.

Here we Construct 2 to 1 Mux and Port Map the 2 to 1 mux component to implement 4 to 1 mux.

implement mux 4 to 1 using mux 2 to 1

VHDL Code for 2 to 1 Mux

library IEEE;

entity sub_module is
port(x,y : in STD_LOGIC;
s: in STD_LOGIC;
z: out STD_LOGIC);
end sub_module ;

architecture Behavioral of sub_module is


process (x,y,s) is
if (s ='0') then
z <= x;
z <= y;
end if;
end process;

end Behavioral;

The 2 to 1 mux can be port mapped in the 4 to 1 mux VHDL code by declaring it as component.

VHDL Code for 4 to 1 mux using 2 to 1 mux

library IEEE;

entity top_module is

S0,S1: in STD_LOGIC;
end top_module ;

architecture Behavioral of top_module is
component sub_module
port(x,y : in STD_LOGIC;
s: in STD_LOGIC;
z: out STD_LOGIC);
end component;
signal m1, m2: std_logic;

c1: sub_module port map(A,B,S0,m1);
c2: sub_module port map(C,D,S0,m2);
c3: sub_module port map(m1,m2,S1,Z);

end Behavioral;

In the above code we implemented positional port mapping technique by mapping at exact port location.

same can be declared with nominal Port mapping as shown below

c1: sub_module port map(A => x, B => y , S0  => s,  m1 => z);
c2: sub_module port map(C => x, D => y, S0 => s, m2 => z);
c3: sub_module port map(m1 => x, m2 => y, S1 => s, Z => z);




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1 Response

  1. Hossein says:

    Hi thank,s

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