Reset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset.
Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input. It can assert and desert a flipflop asynchronously.
DCM provides clocking to all the resources of Xilinx FPGA with advanced feature. Digital Clock Manager DCM integrates advanced clocking capabilities to FPGA global clock distribution network.
It eliminates clock deskewing, Phase shifting, and also act as frequency synthesizer multiply/divide input clock.