VHDL

Tutorial 1: Binary Counter FPGA Implementation

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In this tutorial, We implemented 4 bit binary counter using EDGE Spartan 6 FPGA Kit. It counts at every 0.5 sec. We already designed 4 bit Binary counter for simulation which counts at input clock frequency (20 ns). As a result we can’t visually differentiate the counting sequence with on-board LEDs as it is counting … Read more

BCD to 7 Segment Decoder VHDL Code

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VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design.

For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.

Sequence Detector using Mealy and Moore State Machine VHDL Codes

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Mealy State Machine
The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input.
Moore State Machine
The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.

Carry Select Adder VHDL Code

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carry select adder VHDL Code

Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input ‘0’ and select Sum and carry output from stage 2 ripple carry adder, when carry input ‘1’.

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