BCD to 7 Segment Decoder VHDL Code

VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design.

For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.

Sequence Detector using Mealy and Moore State Machine VHDL Codes

Mealy State Machine
The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input.
Moore State Machine
The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.

Carry Save Adder VHDL Code

carry save adder vhdl code

Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage.  At first stage result carry is not propagated through  addition operation. In order to generate carry, implemented ripple carry adder on stage 2 for carry propagation. Carry Save adder VHDL Code can be constructed by port mapping full adder VHDL Code to 2 stage adder circuit.

×