Digital Clock Manager
DCM provides clocking to all the resources of Xilinx FPGA with advanced feature. Digital Clock Manager DCM integrates advanced clocking capabilities to FPGA global clock distribution network.
It eliminates clock deskewing, Phase shifting, and also act as frequency synthesizer multiply/divide input clock.
The Delay-Locked Loop (DLL) unit provides an on-chip digital deskew circuit that effectively generates clock output signals with a net zero delay. The DLL unit effectively eliminates the delay from the external clock input port to the individual clock loads within the device.
The Phase Shift (PS) unit controls the phase relations of the DCM’s clock outputs to the CLKIN input. The Phase Shift unit shifts the phase of DCM clock output signals by a fixed fraction of the input clock period.
The Digital Frequency Synthesizer (DFS) provides a wide range of output frequencies based on the ratio of two user-defined integers, a Multiplier (CLKFX_MULTIPLY) and a Divisor (CLKFX_DIVIDE).