The amount of time the synchronous input (D) must be stable before the active edge of the clock.
The amount of time the synchronous input (D) must be stable after the active edge of the clock.
If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is said to metastability.
2 thoughts on “Setup Time and Hold Time in FPGA”
Where/How do we need to set this timings in XLINX? Any thoughts please
Ksr, You need to learn timing analysis user guide from xilinx to know how to set timing constraint in Xilinx ISE. Btwn we will soon write an article on the same.