Setup Time and Hold Time in FPGA

Setup Time and Hold Time in FPGA

Setup Time

The amount of time the synchronous input (D) must be stable before the active edge of the clock.

Hold Time

The amount of time the synchronous input (D) must be stable after the active edge of the clock.

Metastability

If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is said to metastability.

setup and hold time

 

2 thoughts on “Setup Time and Hold Time in FPGA

    • Ksr, You need to learn timing analysis user guide from xilinx to know how to set timing constraint in Xilinx ISE. Btwn we will soon write an article on the same.

      Cheers,
      DNA

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