Clock Divider is also known as frequency divider, which divides the input clock frequency and produce output clock. In our case let us take input frequency as 50MHz and divide the clock frequency to generate 1KHz output signal.
VHDL code consist of Clock and Reset input, divided clock as output. Count is a signal to generate delay, Tmp signal toggle itself when the count value reaches 25000. Output produce 1KHz clock frequency.
Reference count values to generate various clock frequency output