Category: FPGA

VHDL Code for Debounce Circuit in FPGA

Debounce Push Button always got the mechanical property of bouncing state at micro sec. The above figure describes the debouncing  output result,  when the Push Button is pressed. When you pull down the push button from high to low state. It bounce back to high and low few times before it settle at proper output. In

Synchronous and Asynchronous Reset VHDL

Reset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset. Asynchronous Reset Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input. It can assert and desert a flipflop asynchronously.

Block RAM and Distributed RAM in Xilinx FPGA

Block RAM: Xilinx FPGA Consist of 2 columns of memory called Block RAM or BRAM. It is a Dual port memory with separate Read/Write port. It can be  configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on. BRAM can be excellent for FIFO implementation. Multiple blocks can be cascaded to create still larger

Setup Time and Hold Time in FPGA

Setup Time The amount of time the synchronous input (D) must be stable before the active edge of the clock. Hold Time The amount of time the synchronous input (D) must be stable after the active edge of the clock. Metastability If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is

Digital Clock manager DCM in Xilinx FPGA

Digital Clock Manager DCM provides clocking to all the resources of Xilinx FPGA with advanced feature. Digital Clock Manager DCM integrates advanced clocking capabilities to FPGA global clock distribution network. It eliminates clock deskewing, Phase shifting, and also act as frequency synthesizer multiply/divide input clock. Clock Deskewing The Delay-Locked Loop (DLL) unit provides an on-chip digital

FPGA Configuration Tutorial

What is FPGA Configuration? The FPGA is made of SRAM (Volatile Memory) so the data configured inside FPGA lost at power Off state. FPGA Configuration is the process of loading the FPGA chip with Configuration data through external devices during power On state. The Method of Configuring FPGA Can be divided in to Master Mode Slave Mode JTAG Mode

FPGA Architecture

What is FPGA? Field-programmable gate array (FPGA) is a device that has array of Configurable logic gates and can be programmed on-board through dedicated Joint Test Action Group (JTAG) or through any other serial/ Parallel non-volatile Memory. FPGA architecture are based on static random-access memory (SRAM) Volatile memory. The Data programmed inside the memory of an FPGA