Setup Time and Hold Time in FPGA

Last updated on October 30th, 2014 at 03:03 pm

Setup Time

The amount of time the synchronous input (D) must be stable before the active edge of the clock.

Hold Time

The amount of time the synchronous input (D) must be stable after the active edge of the clock.

Metastability

If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is said to metastability.

setup and hold time

 

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