June 26, 2014 HomeFPGASetup Time and Hold Time in FPGA Setup Time and Hold Time in FPGA By Admin FPGA 2 Comments Last updated on October 30th, 2014 at 03:03 pmSetup Time The amount of time the synchronous input (D) must be stable before the active edge of the clock. Hold Time The amount of time the synchronous input (D) must be stable after the active edge of the clock. Metastability If either setup time or hold time violates, correct operation of FF is not guaranteed . Then it is said to metastability. Download Post as PDF Tags:hold time, metastability, setup time Digital Clock manager DCM in Xilinx FPGA VHDL Code for Clock Divider (Frequency Divider) Related Posts FPGA Design Flow Synchronous and Asynchronous Reset VHDL FPGA Configuration Tutorial 2 Comments ksr Where/How do we need to set this timings in XLINX? Any thoughts please July 6, 2014 Reply Admin Ksr, You need to learn timing analysis user guide from xilinx to know how to set timing constraint in Xilinx ISE. Btwn we will soon write an article on the same. Cheers, DNA July 9, 2014 Reply Add a Comment Cancel reply Your email address will not be published. Required fields are marked *Comment:*Name:* Email Address:* Website: Notify me of follow-up comments by email. Notify me of new posts by email.