Working with Altera Quartus II Software
Altera Tutorial

Working with Altera Quartus II Software

This Video demonstrate step by step procedure to create new Altera Quartus II Project with Schematics for NAND gate logic...
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Working with Xilinx ISE Software
Xilinx Tutorial

Working with Xilinx ISE Software

This Video demonstrate step by step procedure to create new Xilinx ISE Project with VHDL top module for LED Blinking...
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What is FPGA?
FPGA Video Tutorial

What is FPGA?

After watching this FPGA Basics video you will be able to understand what is FPGA? How to configure FPGA? Difference...
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VHDL Basics Part-8
VHDL Video Tutorial

VHDL Basics Part-8

This Video tutorial introduce basic VHDL to the Beginners. Part-8
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VHDL Basics Part-7
VHDL Video Tutorial

VHDL Basics Part-7

This Video tutorial introduce basic VHDL to the Beginners. Part-7
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VHDL Basics Part-6
VHDL Video Tutorial

VHDL Basics Part-6

This Video tutorial introduce basic VHDL to the Beginners. Part-6
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VHDL Basics Part-5
VHDL Video Tutorial

VHDL Basics Part-5

This Video tutorial introduce basic VHDL to the Beginners. Part-5
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VHDL Basics Part-4
VHDL Video Tutorial

VHDL Basics Part-4

This Video tutorial introduce basic VHDL to the Beginners. Part-4
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VHDL Basics Part-3
VHDL Video Tutorial

VHDL Basics Part-3

This Video tutorial introduce basic VHDL to the Beginners. Part-3
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VHDL Basics Part-2
VHDL Video Tutorial

VHDL Basics Part-2

This Video tutorial introduce basic VHDL to the Beginners. Part-2
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VHDL Basics Part-1
VHDL Video Tutorial

VHDL Basics Part-1

This Video tutorial introduce basic VHDL Tutorial to the Beginners. Objective of this VHDL Tutorial includes VHDL Model Construction Logic...
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Altera FPGA Design Flow Tutorial
FPGA Video Tutorial

Altera FPGA Design Flow Tutorial

This tutorial video describe Altera FPGA Design flow in simple explanation. This video tutorial was originally developed by Bill Kleitz....
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VHDL Code for Debounce Circuit in FPGA
FPGA VHDL

VHDL Code for Debounce Circuit in FPGA

Push Button always got the mechanical property of bouncing state at micro sec. When you pull down the push button from high to low state. It bounce back to high and low few times before it settle at proper output. In order to avoid such bouncing state, we need to create debounce logic circuit.
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Synchronous and Asynchronous Reset VHDL
FPGA VHDL

Synchronous and Asynchronous Reset VHDL

Reset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset. Asynchronous Reset Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input. It can assert and desert a flipflop asynchronously.
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VHDL Code for Binary to BCD Converter
VHDL

VHDL Code for Binary to BCD Converter

Binary to BCD Converter Some times we need to display the output in a seven-segment display. For that purpose we will convert binary to BCD. To translate from binary to BCD, we can employ the shift-and-add-3 algorithm: Left-shift the (n-bit) binary number one bit. If n shifts have taken place, the number has been fully expanded, so exit the algorithm. If the binary value of any of the BCD columns is greater than or equal to 5, add 3. Return to (1).
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Block RAM and Distributed RAM in Xilinx FPGA
FPGA

Block RAM and Distributed RAM in Xilinx FPGA

Block RAM: Xilinx FPGA Consist of 2 columns of memory called Block RAM or BRAM. It is a Dual port memory with separate Read/Write port. It can be  configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on. BRAM can be excellent for FIFO implementation.
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VHDL code for 4-bit binary comparator
VHDL

VHDL code for 4-bit binary comparator

Binary comparator compare two 4-bit binary number. It is also known as magnitude comparator and digital comparator. Analog form comparator is voltage comparator. The functionality of this comparator circuit is, It consist of 3 outputs Greater, Equal and Smaller. If inp-A is greater then inp-B then greater output is high, if both inp-A and inp-B are same then equal output is high, else smaller output is high.
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VHDL Code for 4-bit Adder / Subtractor
VHDL

VHDL Code for 4-bit Adder / Subtractor

This example describes a two input 4-bit adder/subtractor design in VHDL. The design unit multiplexes add and subtract operations with an OP input. 0 input produce adder output and 1 input produce subtractor output.
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VHDL Code for Flipflop – D,JK,SR,T
VHDL

VHDL Code for Flipflop – D,JK,SR,T

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. SR FlipFlop A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown in Figure. Each flip-flop has two outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop.
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VHDL Code for Clock Divider (Frequency Divider)
VHDL

VHDL Code for Clock Divider (Frequency Divider)

Clock Divider is also known as frequency divider, which divides the input clock frequency and produce output clock. In our case let us take input frequency as 50MHz and divide the clock frequency to generate 1KHz output signal. VHDL code consist of Clock and Reset input, divided clock as output. Count is a signal to generate delay, Tmp signal toggle itself when the count value reaches 25000. Output produce 1KHz clock frequency. Reference count values to generate various clock frequency output
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