VHDL code for 1 to 4 Demux

Demultiplexer 1 to 4

Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single input through selection line. It consist of  1 input and 2 power n output. The output data lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to 4 mux with 1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4 Demux described below.

Synchronous and Asynchronous Reset VHDL

Reset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset.

Asynchronous Reset
Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input. It can assert and desert a flipflop asynchronously.

VHDL Code for Binary to BCD Converter

Binary to BCD Converter
Some times we need to display the output in a seven-segment display. For that purpose we will convert binary to BCD.

To translate from binary to BCD, we can employ the shift-and-add-3 algorithm:

Left-shift the (n-bit) binary number one bit.
If n shifts have taken place, the number has been fully expanded, so exit the algorithm.
If the binary value of any of the BCD columns is greater than or equal to 5, add 3.
Return to (1).