VHDL Testbench is important part of VHDL design to check the functionality of Design through simulation waveform. Testbench provide stimulus for design under test DUT or Unit Under Test UUT to check the output result.
A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli that is portable across different simulators. Testbench consist of entity without any IO ports, Design instantiated as component, clock input, and various stimulus inputs.
Component is a reusable VHDL module which can be declared with in another digital logic circuit using Component declaration of the VHDL Code. This helps to implement hierarchical design at ease.
Instead of coding a complex design in single VHDL Code. we can divide the code in to sub modules as component and combine them using Port Map technique.
VHDL Port Map is the Process of mapping the input/ Output Ports of Component in Main Module.
The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are High. Cout is High, when two or more inputs are High. VHDL Code for full adder can also be constructed with 2 half adder Port mapping in to full adder.