VHDL Code for 4 to 2 Encoder
Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling.
VHDL
VHDL Code for 4-Bit Aynchronous Accumulator
Accumulator work similar to the functionality of counter. The main difference is instead increment the counter value by constant, Accumulator add the input value with the current value.
VHDL code for 1 to 4 Demux
Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single input through selection line. It consist of 1 input and 2 power n output. The output data lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to 4 mux with 1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4 Demux described below.
VHDL 4 to 1 Mux (Multiplexer)
Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line through selection line. It consist of 2 power n input and 1 output. The input data lines are controlled by n selection lines.
VHDL Code for Debounce Circuit in FPGA
Push Button always got the mechanical property of bouncing state at micro sec.
When you pull down the push button from high to low state. It bounce back to high and low few times before it settle at proper output. In order to avoid such bouncing state, we need to create debounce logic circuit.
