VHDL Code for Clock Divider ( Frequency Divider )
Clock Divider is also known as frequency divider, which divides the input clock frequency and produce output clock. In our case let us take input frequency as 50Mhz and divide the clock frequency to generate 1Khz output signal. VHDL code consist of Clock and Reset input, divided clock as output. Count is a signal to generate delay, Tmp signal toggle itself when the counter value reaches 25000. Output produce 1Khz clock frequency.
VHDL Code for Clock Divider
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity Clock_Divider is port ( clk,reset: in std_logic; clock_out: out std_logic); end Clock_Divider; architecture bhv of Clock_Divider is signal count: integer:=0; signal tmp : std_logic := '1'; begin process(clk,reset) begin if(reset='0') then count<=0; tmp<='1'; elsif(clk'event and clk='1') then count <=count+1; if (counter = 25000) then tmp <= NOT tmp; count <= 0; end if; end if; clock_out <= tmp; end process; end bhv;