VHDL Code for Clock Divider (Frequency Divider)

Clock Divider is also known as frequency divider, which divides the input clock frequency and produce output clock. In our case let us take input frequency as 50MHz and divide the clock frequency to generate 1KHz output signal.

VHDL code consist of Clock and Reset input, divided clock as output. Count is a signal to generate delay, Tmp signal toggle itself when the count value reaches 25000. Output produce 1KHz clock frequency.

Reference count values to generate various clock frequency output

Count Value      Output Frequency

1                         25MHz

25                       1MHz

50                       500KHz

1000                   25KHz

25000000           1Hz


VHDL Code for Clock Divider

library IEEE;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture bhv of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
if(reset='1') then
elsif(clk'event and clk='1') then
count <=count+1;
if (count = 25000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end bhv;

VHDL Testbench code for VHDL Divider

USE ieee.std_logic_1164.ALL;

ENTITY Tb_clock_divider IS
END Tb_clock_divider;

ARCHITECTURE behavior OF Tb_clock_divider IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Clock_Divider
clk : IN std_logic;
reset : IN std_logic;
clock_out : OUT std_logic

signal clk : std_logic := '0';
signal reset : std_logic := '0';

signal clock_out : std_logic;

-- Clock period definitions
constant clk_period : time := 20 ns;


-- Instantiate the Unit Under Test (UUT)
uut: Clock_Divider PORT MAP (
clk => clk,
reset => reset,
clock_out => clock_out

-- Clock process definitions
clk_process :process
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
wait for 100 ns;
reset <= '1';
wait for 100 ns;
reset <= '0';
end process;


Testbench Waveform for 1Khz Clock divider from 50MHz clock input

clock divider VHDL testbench waveform

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17 Responses

  1. Mike says:

    Why we need tmp signal instead of directly inverting clkout?

  2. Admin says:

    Output can’t be inverted directly and assign to the same output port.. That’s why declared tmp signal and finally assigned to output.

  3. Serge says:

    Hi, i was trying to use your clock, but it keeps sending the error of ‘counter’ not being assigned, any ideas on how to fix it?

    Error (10482): VHDL error at Clock_divider.vhd(24): object “counter” is used but not declared

  4. Rakshith says:

    Pls suggest me program for output y =1 when s=1 for continuous 3 clock pulse… If S changes btwn 3 clk pulse then output should goes low… Sequential circuit

    • Admin says:

      Rakshith, try the following declare count as integer

      if s= ‘1’ then
      count = count + 1;
      if count = 3 then
      count = 0;
      y = ‘1’;
      end if;
      y = ‘0’;
      count = 0;
      end if;

  5. saswata says:

    how do i generate the vhdl test bench code??for the above program…

  6. Admin says:

    Rafer the following post for How to create VHDL Testbench?

    You need to toggle reset from high to low after some delay in testbench code.

    I will update the code with testbench soon.

  7. Paebbels says:

    Your counter does not provide a 1kHz output signal, because it counts 25,001 cycles (0 .. 25k equals 25,001).


  8. mctnnn says:

    How do you calculate output clock frequency, teach me.
    If I want clock out to be 25 MHz, how do I set count=?

  9. David says:

    Hi, i want my clock divide by integer. Like 10, 20 etc. (5MHz, 2.5 MHz) How can i do that? Could you help me?

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