All About FPGA brings you a feature rich development board for FPGA learners community. EDGE Spartan 6 FPGA Development board is the feature rich development board with Spartan 6 FPGA, SPI FLASH, ADC, DAC, LCD, 7 segment Display, Stereo Jack, VGA, PS2, WiFi, Bluetooth. The Board also provides additional interface like CMOS Camera and TFT … Read more
Push Button always got the mechanical property of bouncing state at micro sec.
When you pull down the push button from high to low state. It bounce back to high and low few times before it settle at proper output. In order to avoid such bouncing state, we need to create debounce logic circuit.
Reset Circuit helps to keep the FPGA in to Known State. There are 2 types Resets commonly employed to Reset FPGA. They are Asynchronous and Synchronous Reset.
Asynchronous Reset
Asynchronous Reset circuit is independent of free running clock. Which means Reset circuit got no knowledge of Clock input. It can assert and desert a flipflop asynchronously.
Block RAM:
Xilinx FPGA Consist of 2 columns of memory called Block RAM or BRAM.
It is a Dual port memory with separate Read/Write port.
It can be configured as different data width 16Kx1, 8Kx8, 4Kx4 and so on.
BRAM can be excellent for FIFO implementation.
Setup Time
The amount of time the synchronous input (D) must be stable before the active edge of the clock.
Hold Time
The amount of time the synchronous input (D) must be stable after the active edge of the clock.
Metastability
Chat with us for queries on the EDGE FPGA kit
