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Learn FPGA: EDGE FPGA kits tutorial series

By Support Team / August 27, 2021

This tutorial series consists of learning VHDL programming with vivado design suite using EDGE Spartan 7 FPGA kit and EDGE...

Tags: FPGA Tutorial, vhdl tutorial, vivado design suite tutorial

FPGA Video Tutorial FPGA

Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board

By Support Team / July 11, 2020

In this IoT project, we are Monitoring Temperature, Light Intensity and control the home appliances such as air conditioner and...

Tags: FPGA IoT

1 Reply

FPGA FPGA Video Tutorial

Social distancing with Gesture based door/light control using Edge Artix 7 FPGA board

By Support Team / July 11, 2020

In this project, we have implemented the hand gesture based Door open/close and Light on/off system using Edge Artix 7...

FPGA VHDL

IoT Covid19 updates in 2×16 LCD and VGA Monitor using EDGE Artix 7 FPGA kit

By Support Team / July 6, 2020

This project visualizes the current data of the coronavirus outbreak of India in real-time on a VGA monitor and also...

FPGA FPGA Video Tutorial VHDL

Introduction and Advantages of Digital Sensor Addon for EDGE FPGA kit

By Support Team / April 18, 2020

Digital Sensor Addon card is designed to interface 4 digital sensor modules to EDGE FPGA kits. Those sensor includes 3...

FPGA FPGA Video Tutorial VHDL Xilinx Tutorial

Introducing Motor Drive Addon for EDGE FPGA kit

By Support Team / April 18, 2020

Invent Logics bring you the motor driver interface card with motors and relay module. This motor driver can be directly...

FPGA

FPGA Implementation of Internet of Things (IoT)

By Support Team / December 10, 2018

Internet of Things IoT is the way of connecting physical objects with IP address to the cloud or any other...

1 Reply

FPGA VHDL

Tutorial 3: ALU Structural Modelling FPGA Implementation

By Support Team / November 8, 2018

ALU ALU internally always do multiple operations like addition, subtraction, division and multiplication. We have to specify which result you...

FPGA VHDL

Tutorial 2: BCD to 7 Segment FPGA Implementation

By Support Team / November 4, 2018

EDGE Spartan 6 FPGA Development Board consist of 16 No. of slide switches and 4 digit seven segment display. Lets...

FPGA VHDL

Tutorial 1: Binary Counter FPGA Implementation

By Support Team / November 4, 2018

In this tutorial, We implemented 4 bit binary counter using EDGE Spartan 6 FPGA Kit. It counts at every 0.5...

1 Reply

FPGA

Introducing EDGE Spartan 6 FPGA Development Board!

By Support Team / February 1, 2018

All About FPGA brings you a feature rich development board for FPGA learners community. EDGE Spartan 6 FPGA Development board...

VHDL

BCD to 7 Segment Decoder VHDL Code

By Support Team / July 9, 2017

VHDL Code BCD to 7 Segment Display decoder can be implemented in 2 ways. By simplifying Boolean expression to implement structural design and behavioral design. For constructing BCD to 7 segment display, first construct truth table and simplify them to Boolean expression using K Map and finally build the combinational circuit.

Tags: BCD to seven segment Decoder, VHDL BCD to 7 segment display

6 Replies

VHDL

Sequence Detector using Mealy and Moore State Machine VHDL Codes

By Support Team / July 5, 2017

Mealy State Machine The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine updated without waiting for change in clock input. Moore State Machine The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge.

Tags: Mealy state machine vhdl code, moore state machine vhdl code, sequence detector vhdl

3 Replies

VHDL

Carry Select Adder VHDL Code

By Support Team / June 2, 2016

Carry Select Adder VHDL Code can be Constructed by implementing 2 stage Ripple Carry Adder and multiplexer circuit. Carry Select Adder select the sum and carry output from stage 1 ripple carry adder when carry input '0' and select Sum and carry output from stage 2 ripple carry adder, when carry input '1'.

Tags: VHDL Code for Carry Select Adder

VHDL

Carry Save Adder VHDL Code

By Support Team / May 31, 2016

Carry save adder used to perform 3 bit addition at once. Here 3 bit input (A, B, C) is processed and converted to 2 bit output (S, C) at first stage. At first stage result carry is not propagated through addition operation. In order to generate carry, implemented ripple carry adder on stage 2 for carry propagation. Carry Save adder VHDL Code can be constructed by port mapping full adder VHDL Code to 2 stage adder circuit.

Tags: VHDL Code for Carry Save Adder

VHDL

Carry Look Ahead Adder VHDL Code

By Support Team / May 29, 2016

Carry Look Ahead Adder is fastest adder compared Ripple carry Adder. For the Purpose of carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and generation Carry block. It avoid Carry propagation through each adder. In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then Carry logic using Propagation and generation Block.

Tags: vhdl code for 4-bit carry look ahead adder

2 Replies

VHDL

4 Bit Ripple Carry Adder VHDL Code

By Support Team / May 29, 2016

Ripple Carry Adder adds 2 n-bit number plus carry input and gives n-bit sum and a carry output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry input of next single bit addition. Each single bit addition is performed with full Adder operation (A, B, Cin) input and (Sum, Cout) output. The 4-bit Ripple Carry Adder VHDL Code can be Easily Constructed by Port Mapping 4 Full Adder. The following figure represent the 4-bit ripple carry adder.

Tags: VHDL Code for 4 bit ripple carry adder

1 Reply

VHDL

VHDL Code for 4-bit Ring Counter and Johnson Counter

By Support Team / May 22, 2016

Ring Counter very similar to shift register. At each clock pulse, data at each flipflop shifted to next flipflop with last output is feed back to the input of first flipflop. Also the first flop is set to '1' at the reset state. so it shift bit '1' to next flipflop for each clock input and repeat the sequence as shown below.

Tags: VHDL Johnson Counter, VHDL Ring Counter

VHDL

VHDL Code for 2 to 4 decoder

By Support Team / February 6, 2016

Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-to-8 and 4-to-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code of 2 to 4 decoder can be easily implemented with structural and behavioral modelling.

Tags: VHDL Decoder 2 to 4

8 Replies

VHDL

VHDL Code for 4 to 2 Encoder

By Support Team / February 5, 2016

Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3 and 16-to-4 line configurations. VHDL Code for 4 to 2 encoder can be designed both in structural and behavioral modelling.

Tags: 4 to 2 priority encoder vhdl code, vhdl encoder 4 to 2

3 Replies

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Blog

Learn FPGA: EDGE FPGA kits tutorial series

Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board

Social distancing with Gesture based door/light control using Edge Artix 7 FPGA board

IoT Covid19 updates in 2×16 LCD and VGA Monitor using EDGE Artix 7 FPGA kit

Introduction and Advantages of Digital Sensor Addon for EDGE FPGA kit

Introducing Motor Drive Addon for EDGE FPGA kit

FPGA Implementation of Internet of Things (IoT)

Tutorial 3: ALU Structural Modelling FPGA Implementation

Tutorial 2: BCD to 7 Segment FPGA Implementation

Tutorial 1: Binary Counter FPGA Implementation

Introducing EDGE Spartan 6 FPGA Development Board!

BCD to 7 Segment Decoder VHDL Code

Sequence Detector using Mealy and Moore State Machine VHDL Codes

Carry Select Adder VHDL Code

Carry Save Adder VHDL Code

Carry Look Ahead Adder VHDL Code

4 Bit Ripple Carry Adder VHDL Code

VHDL Code for 4-bit Ring Counter and Johnson Counter

VHDL Code for 2 to 4 decoder

VHDL Code for 4 to 2 Encoder

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EDGE ZYNQ SoC FPGA Kit

Feature rich and high-performance Single Board Computer